View MAX1809EEE_222265.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-2142; Rev 1; 9/02
3A, 1MHz, DDR Memory Termination Supply
General Description
The MAX1809 is a reversible energy flow, constant-offtime, pulse-width modulated (PWM), step-down DC-DC converter. It is ideal for use in notebook and subnotebook computers that require 1.1V to 5V active termination power supplies. This device features an internal PMOS power switch and internal synchronous rectifier for high efficiency and reduced component count. The internal 90m PMOS power switch and 70m NMOS synchronous-rectifier switch easily deliver continuous load currents up to 3A. The MAX1809 accurately tracks an external reference voltage, produces an adjustable output from 1.1V to VIN, and achieves efficiencies as high as 93%. The MAX1809 uses a unique current-mode, constantoff-time, PWM control scheme that allows the output to source or sink current. This feature allows energy to return to the input power supply that otherwise would be wasted. The programmable constant-off-time architecture sets switching frequencies up to 1MHz, allowing the user to optimize performance trade-offs between efficiency, output switching noise, component size, and cost. The MAX1809 features an adjustable soft-start to limit surge currents during startup, a 100% duty-cycle mode for low-dropout operation, and a low-power shutdown mode that disables the power switches and reduces supply current below 1A. The MAX1809 is available in a 28-pin QFN with an exposed backside pad, a 28-pin thin QFN, or a 16-pin QSOP. o Source/Sink 3A o 1% Output Accuracy o Up to 1MHz Switching Frequency o 93% Efficiency o Internal PMOS/NMOS Switches 90m/70m On-Resistance at VIN = 4.5V 110m/80m On-Resistance at VIN = 3V o 1.1V to VIN Adjustable Output Voltage o 3V to 5.5V Input Voltage Range o <1A Shutdown Supply Current o Programmable Constant-Off-Time Operation o Thermal Shutdown o Adjustable Soft-Start Inrush Current Limiting o Output Short-Circuit Protection
Features
MAX1809
Ordering Information
PART MAX1809EGI* MAX1809EEE MAX1809ETI TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 28 QFN 16 QSOP 28 Thin QFN
Applications
DDR Memory Termination Active Termination Buses
*Contact factory for availability.
Pin Configurations
SHDN N.C. LX LX
Typical Operating Circuit
VIN IN MAX1809 VCC SHDN VSET EXTREF TOFF REF SS LX PGND VOUT
TOP VIEW
28
N.C.
27
26
25
24
N.C.
23
N.C. IN LX IN
22
N.C.
1 2 3 4 5 6 7 10 11 12 13 14 8 9
21 20 19
PGND PGND LX LX PGND VCC GND
GND
N.C.
MAX1809
18 17 16 15
FB
SS EXTREF
N.C.
N.C.
N.C.
TOFF
THIN QFN
Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
GND
REF
FB
3A, 1MHz, DDR Memory Termination Supply MAX1809
ABSOLUTE MAXIMUM RATINGS
VCC, IN to GND ........................................................-0.3V to +6V IN to VCC .............................................................................0.3V GND to PGND.....................................................................0.3V SHDN, SS, FB, TOFF, RREF, EXTREF to GND.......................................-0.3V to (VCC + 0.3V) LX Current (Note 1).............................................................4.7A REF Short Circuit to GND Duration ............................Continuous Continuous Power Dissipation (TA = +70C) 28-Pin QFN (derate 20mW/C above +70C; part mounted on 1in2 of 1oz copper) ..............................1.6W 16-Pin QSOP (derate 12.5mW/C above +70C; part mounted on 1in2 of 1oz copper) .................................1W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Note 1: LX has clamp diodes to PGND and IN. If continuous current is applied through these diodes, thermal limits must be observed.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VCC = 3.3V, VEXTREF = 1.1V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Input Voltage Feedback Voltage Accuracy (VFB - VEXTREF) Feedback Load Regulation Error External Reference Voltage Range Reference Voltage Reference Load Regulation PMOS Switch On-Resistance NMOS Switch On-Resistance Current-Limit Threshold Switching Frequency No Load Supply Current Shutdown Supply Current Thermal-Shutdown Threshold Undervoltage Lockout Threshold FB Input Bias Current Off-Time Startup Off-Time On-Time tON (Note 3) 0.35 IFB tOFF RPMOS RNMOS ILIMIT fSW ICC IIN ISHDN VFB VEXTREF VREF IREF = -1A to +10A ILX = 0.5A ILX = 0.5A VIN > VLX (Note 3) fSW = 500kHz fSW = 500kHz SHDN = GND, ICC + IIN Hysteresis = 15C VCC falling, hysteresis = 90mV VFB = VEXTREF + 0.1V RTOFF = 30.1k RTOFF = 110k RTOFF = 499k 2.5 0 0.24 0.9 3.8 1 16 <1 160 2.6 60 0.30 1.0 4.5 4 x tOFF 2.7 250 0.37 1.1 5.2 s s s 15 VIN = 4.5V VIN = 3V VIN = 4.5V VIN = 3V 3.5 SYMBOL VIN,VCC VIN = VCC = 3V to 5.5V, ILOAD = 0, VEXTREF = 1.25V (Note 2) ILOAD = -3A to +3A, VEXTREF = 1.25V VIN = VCC = 3V to 5.5V VREF 0.01 1.078 1.100 0.5 90 110 70 80 4.1 CONDITIONS MIN 3.0 -12 20 VIN 1.7 1.122 2.0 200 250 150 200 4.7 1 TYP MAX 5.5 +12 UNITS V mV mV V V mV m m A MHz mA A C V nA
2
_______________________________________________________________________________________
3A, 1MHz, DDR Memory Termination Supply
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VCC = 3.3V, VEXTREF = 1.1V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SS Source Current SS Sink Current SHDN Input Current SHDN Logic Levels Maximum Output RMS Current VIL VIH IOUT(RMS) 2 3.1 SYMBOL ISS ISS VSS = 1V V SHDN = 0, VCC CONDITIONS MIN 4 1 -1 TYP 5 50 +1 0.8 MAX 6 UNITS A mA A V ARMS
MAX1809
ELECTRICAL CHARACTERISTICS
(VIN = VCC = 3.3V, VEXTREF = 1.1V, TA = -40C to +85C, unless otherwise noted.) (Note 4)
PARAMETER Input Voltage Feedback Voltage Accuracy (VFB - VEXTREF) External Reference Voltage Range Reference Voltage PMOS Switch On-Resistance NMOS Switch On-Resistance Current-Limit Threshold FB Input Bias Current Off-Time VEXTREF VREF RPMOS RNMOS ILIMIT IFB tOFF ILX = 0.5A ILX = 0.5A VIN > VLX VFB = VEXTREF + 0.1V RTOFF = 110k 0.85 VIN = 4.5V VIN = 3V VIN = 4.5V VIN = 3V 3.3 SYMBOL VIN, VCC VIN = VCC = 3V to 5.5V, ILOAD = 0, VEXTREF = 1.25V VIN = VCC = 3 V to 5.5V CONDITIONS MIN 3.0 -24 VREF 0.01V 1.067 TYP MAX 5.5 +24 VIN 1.9V 1.133 200 250 150 200 4.9 300 1.15 UNITS V mV V V m m A nA s
Note 2: The output voltage will have a DC-regulation level lower than the feedback error comparator threshold by 50% of the ripple. Note 3: Recommended operating frequency, not production tested. Note 4: Specifications from 0C to -40C are guaranteed by design, not production tested.
_______________________________________________________________________________________
3
3A, 1MHz, DDR Memory Termination Supply MAX1809
Typical Operating Characteristics
(Circuit of Figure 1, VOUT = 1.25V, for VIN = 5V: L = 1H, RTOFF = 130k; for VIN = 3.3V: L = 0.68H, RTOFF = 73.2k.)
EFFICIENCY vs. OUTPUT CURRENT (SOURCING)
MAX1809 toc01
EFFICIENCY vs. OUTPUT CURRENT (SINKING)
MAX1809 toc02
NORMALIZED OUTPUT ERROR vs. OUTPUT CURRENT
-0.2 NORMALIZED OUTPUT ERROR (%) -0.6 -1.0 -1.4 -1.8 -2.2 -2.6 -3.0 VIN = 5V VIN = 3.3V
MAX1809 toc03
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 0 1 2 OUTPUT CURRENT (A) 3 VIN = 5V, VOUT = 2.5V VIN = 3.3V, VOUT = 1.25V VIN = 5V, VOUT = 1.25V RDROOP = 0
95 90 85 EFFICIENCY (%) 80 75 70 65 60 55 50 0
VIN = 5V, VOUT = 2.5V
RDROOP = 0
VIN = 5V, VOUT = 1.25V VIN = 3.3V, VOUT = 1.25V
1 2 OUTPUT CURRENT (A)
3
-3
-2
-1
0
1
2
3
OUTPUT CURRENT (A)
NO-LOAD SUPPLY CURRENT vs. SUPPLY VOLTAGE
NO-LOAD SUPPLY CURRENT (IIN + ICC (mA)) 24 20 16 12 8 4 0 0 1 2 3 VIN (V) 4 5 6
MAX1809 toc04
OFF-TIME vs. RTOFF
4.5 4.0 3.5 tOFF (s) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 50 100 150 200 250 300 350 400 450 500 RTOFF (k) 0 -3 -2
MAX1809 toc05
SWITCHING FREQUENCY vs. OUTPUT CURRENT
VIN = 3.3V
MAX1809 toc06
5.0
1200 1000 FREQUECNY (kHz) 800 600 400 200 VIN = 5V
-1 0 1 OUTPUT CURRENT (A)
2
3
STARTUP AND SHUTDOWN
MAX1809 toc07
LOAD-TRANSIENT RESPONSE
IIN 1A/div RDROOP = 0
MAX1809 toc08
VOUT
(AC-COUPLED)
0A VSHDN 5V/div VOUT 1V/div 0V 0V 1ms/div VIN = 3.3V, ROUT = 0.5 VSS 2V/div 10s/div VEXTREF = 1.25V, VIN = 3.3V, IOUT = -2A to +2A to -2A 0A
50mV/div
0V
0V
V(LX) 5V/div IOUT 5A/div
4
_______________________________________________________________________________________
3A, 1MHz, DDR Memory Termination Supply
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VOUT = 1.25V, for VIN = 5V: L = 1H, RTOFF = 130k; for VIN = 3.3V: L = 0.68H, RTOFF = 73.2k.)
LOAD-TRANSIENT RESPONSE
RDROOP 12m
MAX1809 toc09
MAX1809
LINE-TRANSIENT RESPONSE
MAX1809 toc10
VOUT
(AC-COUPLED)
VOUT
(AC-COUPLED)
50mV/div VIN 2V/div
50mV/div
0V
V(LX) 5V/div IOUT 5A/div
0A
0V 10s/div VEXTREF = 1.25V, VIN = 3.3V, IOUT = -2A to +2A to -2A 20s/div IOUT = 2A, VIN = 5V to 3.3V to 5V
SWITCHING WAVEFORMS (SOURCING)
MAX1809 toc11
SWITCHING WAVEFORMS (SINKING)
MAX1809 toc12
VOUT
(AC-COUPLED)
VOUT (AC-COUPLED) 50mV/div
50mV/div I(LX) 2A/div 0A 0V 0A
I(LX) 2A/div
V(LX) 5V/div 400ns/div IOUT = 2A, VIN = 5V
0V 400ns/div IOUT = -2A, VIN = 5V
V(LX) 5V/div
_______________________________________________________________________________________
5
3A, 1MHz, DDR Memory Termination Supply MAX1809
Pin Description
PIN (QFN) 1, 5, 10, 11, 12, 22, 24, 26, 28 2, 4 PIN (QSOP) -- 2, 4 NAME N.C. IN FUNCTION No Connection. Not internally connected. Supply Voltage Input for the Internal PMOS Power Switch. Not internally connected. Externally connect all pins for proper operation. Inductor Connection. Connection for the drains of the PMOS power switch and NMOS synchronous-rectifier switch. Connect the inductor from this node to the output filter capacitor and load. Not internally connected. Externally connect all pins for proper operation. Soft-Start. Connect a capacitor from SS to GND to limit inrush current during startup. External Reference Input. Feedback input regulates to VEXTREF. The PWM controller remains off until EXTREF is greater than REF. Off-Time Select Input. Sets the PMOS power switch constant-off-time. Connect a resistor from TOFF to GND to adjust the PMOS switch off-time. Feedback Input. Connect directly to output for fixed-voltage operation or to a resistive-divider for adjustable operating modes. Analog Ground. Connect exposed backside pad and corner tabs to analog GND. Reference Output. Bypass REF to GND with a 1F capacitor. Tie to GND (pin 13 QFN; pin 9 QSOP) Analog Supply Voltage Input. Supplies internal analog circuitry. Bypass VCC with a 10 and 2.2F low-pass filter (see Figure 1). Power Ground. Internally connected to the internal NMOS synchronousrectifier switch. Shutdown Control Input. Drive SHDN low to disable the reference, control circuitry, and internal MOSFETs. Drive high or connect to VCC for normal operation.
3, 18, 19, 23, 25
3, 14, 16
LX
6 7 8 9 13, backside pad, corner tabs 14 15 16 17, 20, 21
5 6 7 8 9 10 11 12 13, 15
SS EXTREF TOFF FB GND REF GND VCC PGND
27
1
SHDN
Detailed Description
The MAX1809 synchronous, current-mode, constantoff-time, PWM DC-DC converter steps down input voltages of 3V to 5.5V to an adjustable output voltage from 1.1V to VIN, as set by the voltage applied at EXTREF. It sources and sinks up to 3A of output current. Internal switches composed of a 90m PMOS power switch and a 70m NMOS synchronous-rectifier switch improve efficiency, reduce component count, and eliminate the need for an external Schottky diode across the synchronous switch. The MAX1809 operates in a constant-off-time mode under all loads. A single resistor-programmable constant-off-time control sets switching frequencies up to 1MHz, allowing the user to optimize performance trade6
offs in efficiency, switching noise, component size, and cost. When power is drawn from a regulated supply, constant-off-time PWM architecture essentially provides constant-frequency operation. This architecture has the inherent advantage of quick response to line and load transients. The MAX1809's current-mode, constant-offtime PWM architecture regulates the output voltage by changing the PMOS switch on-time relative to the constant off-time.
Constant-Off-Time Operation
In the constant-off-time architecture, the FB voltage comparator turns the PMOS switch on at the end of each off-time, keeping the device in continuous-conduction mode. The PMOS switch remains on until the
_______________________________________________________________________________________
3A, 1MHz, DDR Memory Termination Supply MAX1809
VIN IN 33F 10 VCC 2.2F SHDN VDDQ (2.5V) 10k 1000pF VSET EXTREF TOFF RTOFF 10k VSSQ 1000pF MAX1809 LX PGND GND FB REF
L
RDROOP
VOUT =
(VDDQ) 2
270F 2V 15m
1F SS 0.01F
FOR VIN = 5V: L = 1H, RTOFF = 130k FOR VIN = 3.3V: L = 0.68H, RTOFF = 73.2k
Figure 1. Typical Application Circuit
feedback voltage exceeds the external reference voltage (VEXTREF) or the positive current limit is reached. When the PMOS switch turns off, it remains off for the programmed off-time (tOFF). To control the current under short-circuit conditions, the PMOS switch remains off for approximately 4 tOFF when VFB < VEXTREF / 4.
a second mode as a synchronous boost, taking power from the output and returning it to the input. Junction-to-ambient thermal resistance, JA, is highly dependent on the amount of copper area immediately surrounding the IC leads. The MAX1809 QFN package has 1in2 of copper area and a thermal resistance of 50C/W with no forced airflow. The MAX1809 16-pin QSOP evaluation kit has 0.5in2 of copper area and a thermal resistance of 80C/W with no forced airflow. Airflow over the board significantly reduces the junctionto-ambient thermal resistance. For heat sinking purposes, it is essential to connect the exposed backside pad of the QFN package to a large analog ground plane.
Thermal Resistance
Synchronous Rectification
In a stepdown regulator without synchronous rectification, an external Schottky diode provides a path for current to flow when the inductor is discharging. Replacing the Schottky diode with a low-resistance NMOS synchronous switch reduces conduction losses and improves efficiency. The NMOS synchronous-rectifier switch turns on following a short delay (approximately 50ns) after the PMOS power switch turns off, thus preventing cross-conduction or "shoot-through." In constant-off-time mode, the synchronous-rectifier switch turns off just prior to the PMOS power switch turning on. While both switches are off, inductor current flows through the internal body diode of the NMOS switch.
Shutdown
Drive SHDN to a logic-level low to place the MAX1809 in low-power shutdown mode and reduce supply current to less than 1A. In shutdown, all circuitry and internal MOSFETs turn off, so the LX node becomes high impedance. Drive SHDN to a logic-level high or connect to VCC for normal operation.
Current Sourcing and Sinking
By operating in a constant-off-time, pseudo-fixed-frequency mode, the MAX1809 can both source and sink current. Depending on the output current requirement, the circuit operates in two modes. In the first mode the output draws current and the MAX1809 behaves as a regular buck controller, sourcing current to the output from the input supply rail. However, when the output is supplied by another source, the MAX1809 operates in
Power Dissipation
Power dissipation in the MAX1809 is dominated by conduction losses in the two internal power switches. Power dissipation due to charging and discharging the gate capacitance of the internal switches (i.e., switching losses) is approximately: PD(CAP) = C VIN2 fSW
_______________________________________________________________________________________
7
3A, 1MHz, DDR Memory Termination Supply MAX1809
where C = 2.5nF and fSW is the switching frequency. Resistive losses in the two power switches are approximated by: PD(RES) = IOUT2 RPMOS where RPMOS is the on-resistance of the PMOS switch. The junction-to-ambient thermal resistance required to dissipate this amount of power is calculated by: JA = (TJ,MAX - TA,MAX) / (PD(CAP) + PD(RES)) where: JA = junction-to-ambient thermal resistance TJ,MAX = maximum junction temperature TA,MAX = maximum ambient temperature
Setting the Output Voltage
The output voltage of the MAX1809 is set by an external voltage applied to the EXTREF pin. This can come directly from another voltage source or external reference. As an active termination supply in DDR applications (see Active Bus Termination in the Applications Information section), the output of the MAX1809 is regulated at half the DDR supply voltage. In mobile systems, the DDR supply voltage is 2.5V, and the termination voltage is 1.25V 40mV. To regulate to 1.25V, an external divide-by-2 resistor network is placed across the DDR supply voltage to generate 1.25V. This 1.25V is connected to EXTREF, which sets the output voltage of the MAX1809. When FB is directly tied to the output (Figure 5), the output voltage range is limited by the external reference's input voltage limits (see EC table). External reference may not be set within 1.7V of the minimum supply voltage. VEXTREF should be limited to less than 1.4V for 3.3V input voltage. Failure to comply can cause the part to operate abnormally and may cause part damage. Alternatively, the output can be adjusted up to VIN by connecting FB to a resistor-divider between the output voltage and ground (Figure 6). Use 50k for R1. R2 is given by: V R2 = R1 OUT - 1 VEXTREF
Design Procedure
For typical applications, use the recommended component values in Figure 1. For other applications, take the following steps: 1) Select the desired PWM-mode switching frequency. See Figure 4 for maximum operating frequency. 2) Select the constant off-time as a function of input voltage, output voltage, and switching frequency. 3) Select RTOFF as a function of off-time. 4) Select the inductor as a function of output voltage, off-time, and peak-to-peak inductor current.
0.01F SS VIN 2.2F VCC FB IN VIN (3.0V TO 5.5V) CIN CERAMIC
MAX1809
CURRENT SENSE
EXTREF
PWM LOGIC AND DRIVERS
LX
L
SHDN REF 1F GND RTOFF PGND
COUT
REF
TIMER
Figure 2. Functional Diagram 8 _______________________________________________________________________________________
3A, 1MHz, DDR Memory Termination Supply MAX1809
VIN
1400 1200 OPERATING FREQUENCY (kHz) 1000 VOUT = 2.5V 800 600 400 200
SYNCHRONOUS BUCK MODE (SOURCING CURRENT)
ISOURCE
VOUT
VOUT = 1.25V
0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VIN (V)
VIN
Figure 4. Maximum Recommended Operating Frequency vs. Input Voltage
ISINK VSOURCE > VOUT
VPMOS = the voltage drop across the internal PMOS power switch |IOUT RPMOS| VNMOS = the voltage drop across the internal NMOS synchronous-rectifier switch |I OUT RNMOS|
SYNCHRONOUS BOOST MODE (SINKING CURRENT)
Figure 3. Sourcing and Sinking Capabilities of the MAX1809
fSW = switching frequency Make sure that tON and tOFF are greater than 400ns when sourcing current. Select RTOFF according to the formula: RTOFF = (tOFF - 0.07s) (117k /1.00s) Recommended values for RTOFF range from 36k to 430k for off-times of 0.4s to 4s. When sinking current, the switching frequency increases due to the on-resistances of the internal switches adding to the voltage across the inductor, reducing the on-time. Calculate tON when sinking current using the equation: VOUT - VNMOS t ON = t OFF VIN - VOUT + VPMOS Check that tON in the current sinking mode is greater than 350ns.
Programming the Switching Frequency and Off-Time and On-Time
The MAX1809 features a programmable PWM-mode switching frequency, which is set by the input and output voltage and the value of RTOFF, connected from TOFF to GND. RTOFF sets the PMOS power switch offtime in PWM mode. Use the following equation to select the off-time while sourcing current according to the desired switching frequency in PWM mode: t OFF =
(VIN - VOUT - VPMOS ) fSW (VIN - VPMOS + VNMOS )
where: tOFF = the programmed off-time VIN = the input voltage VOUT = the output voltage
Inductor Selection
The key inductor parameters must be specified: inductor value (L) and peak current (IPEAK). The following equation includes a constant, denoted as LIR, which is the ratio of peak-to-peak inductor AC current (ripple current)
9
_______________________________________________________________________________________
3A, 1MHz, DDR Memory Termination Supply MAX1809
to maximum DC load current. A higher value of LIR allows smaller inductance but results in higher losses and ripple. A good compromise between size and losses is found at approximately a 25% ripple current to load current ratio (LIR = 0.25). L= Stable operation requires the correct output filter capacitor. When choosing the output capacitor, ensure that: COUT t OFF x 79FV / s VOUT
(ISOURCE - ISINK ) x LIR (VOUT x tOFF )
2xL
(VOUT
x t OFF )
The peak inductor current at full load is calculated by: IPEAK = IOUT +
In applications where the output is subject to large load transients, the output capacitor's size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: RESR VOUT / IOUT(MAX) The actual microfarad capacitance value required is defined by the physical size needed to achieve low ESR, and by the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR, size, and voltage rating rather than by capacitance value (this is true of tantalums, OS-CONs, and other electrolytics). When using low-capacity filter capacitors such as ceramic or polymer types, capacitor size is usually determined by the capacity needed to prevent VSAG and VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising-load edge is no longer a problem. The amount of overshoot and undershoot due to stored inductor energy can be calculated as: VSOAR = L IOUT2 /(2 COUT VOUT) VSAG = L IOUT2/[2 COUT (VIN - VOUT)]
where IOUT is the maximum source or sink current. Choose an inductor with a saturation current at least as high as the peak inductor current. Additionally, verify the peak inductor current while sourcing output current (IOUT = ISOURCE) does not exceed the positive current limit. The inductor selected should exhibit low losses at the chosen operating frequency.
Input Capacitor Selection
The input filter capacitor reduces peak currents and noise at the voltage source. Use a low-ESR and lowESL capacitor located no further than 5mm from IN. Select the input capacitor according to the RMS input ripple-current requirements and voltage rating: V OUT x (VIN IRIPPLE = IOUT VIN
-
VOUT )
Soft-Start
Soft-start allows a gradual increase of the internal current limit to reduce input surge currents at startup and at exit from shutdown. A timing capacitor, CSS, placed from SS to GND sets the rate at which the internal current limit is changed. Upon power-up, when the device comes out of undervoltage lockout (2.6V typ) or after the SHDN pin is pulled high, a 4A constant current source charges the soft-start capacitor and the voltage on SS increases. When the voltage on SS is less than approximately 0.7V, the current limit is set to zero. As the voltage increases from 0.7V to approximately 1.8V, the current limit is adjusted from 0V to the current-limit threshold (see the Electrical Characteristics). The voltage across the softstart capacitor changes with time according to the equation: VSS = 4A x t CSS
where IRIPPLE = input RMS current ripple.
Output Capacitor Selection
The output filter capacitor affects the output voltage ripple, output load-transient response, and feedback loop stability. The output filter capacitor must have low enough ESR to meet output ripple and load transient requirements, yet have high enough ESR to satisfy stability requirements. Also, the capacitance value must be high enough to guarantee stability and absorb the inductor energy going from a full-load sourcing to fullload sinking condition without exceeding the maximum output tolerance. For stable operation, the MAX1809 requires a minimum feedback ripple voltage of VRIPPLE 1% VEXTREF. The minimum ESR of the output capacitor should be: RESR > 1% (L / tOFF)
10
______________________________________________________________________________________
3A, 1MHz, DDR Memory Termination Supply MAX1809
VOUT = VEXTREF LX VDDQ
LX MAX1809 EXTREF
VOUT R2
MAX1809
VEXTREF (1.1V VEXTREF VIN - 1.7V)
EXTREF
FB
FB R1
R2 = R1[(VOUT / VEXTREF) - 1]
Figure 5. Adjusting the Output Voltage Using EXTREF
Figure 6. Adjusting the Output Voltage at FB
The output current limit during soft-start varies with the voltage on the soft-start pin, SS, according to the equation: ILIM(SS) = VSS - 0.7V x ILIMIT 1.1V
where I LIMIT is the current-limit threshold from the Electrical Characteristics. The constant-current source stops charging once the voltage across the soft-start capacitor reaches 1.8V.
careful component placement, and correct routing of traces using appropriate trace widths. The following points are in order of decreasing importance: 1) Minimize switched-current and high-current ground loops. Connect the input capacitor's ground, the output capacitor's ground, and PGND close together. Connect the resulting PGND plane to GND at only one point. 2) Connect the input filter capacitor less than 5mm away from IN. The connecting copper trace carries large currents and must be at least 1mm wide, preferably 2.5mm. 3) Place the LX node components as close together and as near to the device as possible. This reduces resistive and switching losses as well as noise. 4) Ground planes are essential for optimum performance. In most applications, the circuit is located on a multilayer board and full use of the four or more layers is recommended. For heat dissipation, connect the exposed backside pad of the QFN package to a large analog ground plane, preferably on a surface of the board that receives good airflow. If the ground plane is located on the top layer, make use of the N.C. pins adjacent to GND to lower thermal resistance to the ground plane. If the ground is located elsewhere, use several vias to lower thermal resistance. Typical applications use multiple ground planes to minimize thermal resistance. Avoid large AC currents through the analog ground plane.
Applications Information
Frequency Variation with Output Current
The operating frequency of the MAX1809 is determined primarily by t OFF (set by R TOFF), V IN, and V OUT as shown in the following formula: fSW = t OFF (VIN - VPMOS + VNMOS )
(VIN - VOUT - VPMOS )
However, as the output current increases, the voltage drop across the NMOS and PMOS switches increases and the voltage across the inductor decreases. This causes the frequency to drop. Assuming R PMOS = RNMOS, the change in frequency can be approximated with the following formula: fSW = IOUT x RPMOS (VIN x tOFF )
Voltage Positioning
In applications where the load transients are extremely fast (>10A/s), the total output capacitance has to be large enough to handle the VSAG and VSOAR requirements while keeping within the output tolerance limits. Voltage positioning reduces the total amount of output capacitance needed to meet a given transient response requirement. With voltage positioning, the
11
where RPMOS is the resistance of the internal MOSFETs (90m typ).
Circuit Layout and Grounding
Good layout is necessary to achieve the MAX1809's intended output power level, high efficiency, and low noise. Good layout includes the use of ground planes,
______________________________________________________________________________________
3A, 1MHz, DDR Memory Termination Supply MAX1809
output regulates at a slightly lower voltage under a given load, allowing more voltage headroom as the load changes suddenly to zero or to the opposite polarity (sinking mode). By utilizing the full-voltage tolerance limits, the total output capacitance can be reduced and the capacitor's ESR can be increased. Choose RDROOP such that the output voltage at the maximum load current, including ripple, is just above the lower limit of the output tolerance. RDROOP IOUT(MAX) VOUT(TYP) - VOUT(MIN)(VRIPPLE / 2) Voltage positioning results in some loss in efficiency due to the power dissipated in RDROOP. The maximum power loss is given by RDROOP IOUT(MAX)2. RDROOP must be able to handle this power.
SHDN 0 1.8V VSS (V) 0 ILIMIT ILIMIT (A) 0 t 0.7V
Figure 7. Soft-Start Current Limit Over Time
VDDQ
Ceramic Output Capacitor Applications
Ceramic capacitors have advantages and disadvantages. They have ultra-low ESR and are noncombustible, relatively small, and nonpolarized. They are also expensive and brittle, and their ultra-low ESR characteristic can result in excessively low output-voltage ripple (affecting stability in nonvoltage-positioned circuits). In addition, their relatively low capacitance value can cause output overshoot when going abruptly from full-load sourcing to full-load sinking conditions, unless the inductor value can be made small (high switching frequency), or there are some bulk tantalum or electrolytic capacitors in parallel to absorb the stored energy in the inductor. In some cases, there may be no room for electrolytics, creating a need for a DC-DC design that uses nothing but ceramics. The MAX1809 can take full advantage of the small size and low ESR of ceramic output capacitors in a voltagepositioned circuit. The addition of the positioning resistor increases the ripple at FB, satisfying the minimum feedback ripple voltage requirement. Output overshoot (V SOAR) determines the minimum output capacitance requirement (see the Output Capacitor Selection). Often the switching frequency is set as high as possible (near 1000kHz), and the inductor value is reduced to minimize the energy transferred from inductor to capacitor during load-step recovery.
LINE RECEIVERS
COMMON BUS TERMINATION RESISTOR VOUT (MAX1809)
+ V /2 = VTT - DDQ
Figure 8. Active Bus Termination
source capable of absorbing energy, the voltage at the input will rise. This voltage can violate the absolute maximum voltage at the input of the MAX1809 and destroy the part. This occurs when sinking current because the topology acts as a boost converter, pumping energy from the low-voltage side (the output), to the high-voltage side (the input). The input (high-voltage side) voltage is limited only by the clamping effect of the voltage source connected there. To avoid this problem, make sure the input to the MAX1809 is connected to a low impedance, two quadrant supply or that the load (excluding the MAX1809) connected to that supply consumes more power than the amount being transferred from the MAX1809 output to the input.
Active Bus Termination
DDR memory architecture is a high-speed system that clocks data on both the rising and falling edges of the clock. This increases the data rate, and at the same time increases the system power dissipation. Highspeed digital logic requires termination of the buses to minimize ringing and reflection. Using an active termination scheme reduces the power dissipation of the bus. By connecting the termination resistors to a supply voltage (VTT) that is half the memory voltage (VDDQ),
Input Source
The output of the MAX1809 can accept current due to the reversible properties of the buck and the boost converter. When voltage at the output of the MAX1809 (low-voltage port) exceeds or equals the output set voltage the flow of energy reverses, going from the output to the input (high-voltage port). If the input (highvoltage port) is not connected to a low-impedance
12
______________________________________________________________________________________
3A, 1MHz, DDR Memory Termination Supply MAX1809
INPUT VOLTAGE (3V TO 5.5V) CIN 10 VCC 2.2F SHDN SHDN EXTREF MAX1809 PGND GND VDDQ (2.5V) 10k 0.1F L IN LX FB COUT SHDN (a) 2N7002 (b)
VTT = VDDQ/2
10k VSSQ
0.1F
Figure 9. Discharging the Output of the MAX1809 in Shutdown
Pin Configurations (continued)
INPUT VOLTAGE (3V TO 5.5V) CIN 10 VCC 2.2F SHDN SHDN MAX1809 L IN LX FB 100 PGND COUT VTT =VDDQ/2
TOP VIEW
SHDN 1 IN 2 LX 3 IN 4 16 LX 15 PGND 14 LX
MAX1809
13 PGND 12 VCC 11 GND 10 REF 9 GND
GND
SS 5
SS 0.01F
EXTREF 6 TOFF 7 FB 8
Figure 10. Starting the MAX1809 in Sinking Mode with VOUT >VEXTREF
QSOP
the dissipation in the termination resistor is halved compared to a termination scheme that connects the resistive terminators to ground. The VTT supply requires that it regulates to half the memory voltage (V DDQ ), tracks the changes of the memory voltage, and is able to source and sink current depending on the state of the bus. These requirements are met in the MAX1809.
Discharging the Output in Shutdown
When SHDN is brought low after the controller has been on for a while, the output may remain high if there is no leakage or discharge path to bring the output down. For DDR memory systems, keeping VTT at 1.25V when VDDQ (2.5V) is shut down violates the DDR specifications. This can result in the bus latching if the sys-
tem is subsequently turned on or possibly damaging the memory subsystem. When using the MAX1809 to generate the VTT output of 1.25V, several circuits are recommended to discharge the output when the MAX1809 is shut down. These are shown in Figure 9. Solution (a) is a diode added from VTT to VDDQ so that VTT is discharged when VDDQ goes low. Alternatively, solution (b) uses a small signal transistor to discharge VTT when the MAX1809 is shut down.
Startup in Sinking Mode
The MAX1809 will not startup until the feedback voltage is made less than the external reference voltage when power is applied or when the part is exiting shutdown. In applications that cannot guarantee VFB < VEXTREF
13
______________________________________________________________________________________
3A, 1MHz, DDR Memory Termination Supply MAX1809
before startup, a 100 resistor should be added in the feedback path, and a diode from FB to SS as shown in Figure 10. SS will keep FB low during the startup sequence, ensuring that the MAX1809 enters into PWM mode and begins sinking current. See the Soft-Start Sink Current specification in the Electrical Characteristics for resistor selection.
Chip Information
TRANSISTOR COUNT: 3662
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
14
______________________________________________________________________________________
32L QFN .EPS
3A, 1MHz, DDR Memory Termination Supply
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX1809
______________________________________________________________________________________
15
3A, 1MHz, DDR Memory Termination Supply MAX1809
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
16
______________________________________________________________________________________
3A, 1MHz, DDR Memory Termination Supply
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN 5x5x0.8 .EPS
MAX1809
0.15 C A
D2
C L
D
b D2/2
0.10 M C A B
PIN # 1 I.D.
D/2
0.15 C B
k
PIN # 1 I.D. 0.35x45
E/2 E2/2 E (NE-1) X e
C L
E2
k L
DETAIL A
e (ND-1) X e
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0140
C
1 2
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0140
C
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX1809EEE

	To Download MAX1809EEE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .